Fraunhofer IKTS / May 26, 2025 - May 28, 2025
17th VDE ITG MN 5.6 Symposium “f(ast)WLR, Wafer Level Reliability, Reliability Simulation & Qualification”

The VDE ITG MN 5.6 group cordially invites experts and newcomers to the field of semiconductor reliability to the 17th VDE ITG MN 5.6 symposium “f(ast)WLR, Wafer Level Reliability, Reliability Simulation & Qualification” at the Fraunhofer IKTS in Dresden – this year with the focus topic: “Chiplets & their usage in fWLR methodology”.
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