Events

The VDE ITG MN 5.6 group cordially invites experts and newcomers to the field of semiconductor reliability to the 17th VDE ITG MN 5.6 symposium “f(ast)WLR, Wafer Level Reliability, Reliability Simulation & Qualification” at the Fraunhofer IKTS in Dresden – this year with the focus topic: “Chiplets & their usage in fWLR methodology”.

Europe's semiconductor industry is on the move, the transformation in the automotive industry is in crisis, the threat of cyber attacks is increasing and geostrategic upheavals are influencing product designs and entire supply chains: all of this is placing growing demands on the reliability of electronic components and converted electronic system components. Proven reliability standards are becoming obsolete, and new testing and validation methods, tools and models are coming into focus. In fact, the need for change also offers opportunities.

The ITG Symposium provides a forum for German-speaking and European semiconductor companies, universities and research institutions to exchange ideas in the field of semiconductor (process) reliability, reliability-enhancing design and operating methods, and their simulation.

Other topics include methods and procedures of manufacturing process monitoring, their reuse in extended use in chip-internal monitoring, both in manufacturing and in the field – thus bringing together disciplines from qualification, manufacturing monitoring, failure analysis and chip and system design.

Another focus is reporting on worldwide standardization activities and trends. At the ITG symposium, standards from organizations such as JEDEC, AEC and IEC will be presented and discussed, and contributions to standardization committees will be prepared.